Charge-coupled device (CCD) image sensors typically include an array of photosensitive areas that collect charge carriers in response to illumination. The collected charge is subsequently transferred from the array of photosensitive areas and converted to a voltage from which an image may be reconstructed by associated circuitry. FIG. 1 depicts a conventional interline CCD image sensor 100 that contains an array of photosensitive areas 110 (each of which may include or consist essentially of a photodiode, photodetector, photocapacitor, or photoconductor) arranged in columns. A vertical CCD (VCCD) 120 is disposed next to each column of photosensitive areas 110, and the VCCDs 120 are connected to a horizontal CCD (HCCD) 130. Following an exposure period, charge is transferred from the photosensitive areas 110 into the VCCDs 120, which subsequently shift the charge, row-by-row in parallel, into the HCCD 130. The HCCD then transfers the pixel charge serially to output circuitry, e.g., an output charge-sensing amplifier 140. The resulting data is then typically digitized, and the digitized image is displayed on a display or stored in a storage unit.
The amount of time required to propagate a voltage signal to the center of an interline CCD image sensor increases with increasing sensor size, because both the total gate capacitance for each vertical clock (CV1, CV2, . . . ) and the effective internal resistance for each vertical clock (RV1, RV2, . . . ) tend to increase as a function of the area of the image sensor. The vertical clock signals are carried upon gates running across the VCCDs (not shown in FIG. 1; see FIG. 2) that are sequentially biased to control the flow of pixel charge within the VCCDs. The characteristic time to propagate a voltage signal to the center of the image sensor may be expressed as τV1, τV2, . . . where τVx=αRVxCVx and α is a numerical constant that depends on the details of the image sensor layout and the functional form used to describe the time-varying signal near the center of the imager. (V1, V2, etc. refer to vertical gate 1, vertical gate 2, etc.)
The vertical clock gates are typically formed of polysilicon, which when doped has a reasonably low resistivity (i.e., a length- and cross-sectional-area-independent measure of resistance to current flow), at least for small image sensors in which signals are not required to travel significant distances. One conventional technique that reduces the effective internal resistance for each vertical clock is “strapping” the polysilicon gates with metal lightshield in a column pattern, i.e., electrically connecting each gate to a metal line (having a lower resistivity) such that signals travelling along the gate encounter less resistance and propagate more quickly. In the standard configuration, the lightshield is electrically connected to a metal line near the top and bottom of the pixel array, as illustrated in FIG. 2.
FIG. 2 illustrates a conventional lightshield strapping pattern that reduces the internal resistance for the vertical clocks for an interline CCD image sensor 200. The figure depicts a “single-wire” layout in which metal strapping lines that reduce the resistance of the VCCD gates are connected to a bus line (which carries control signals for operating the VCCD phases) at the periphery of the imager, e.g., at the top or bottom. For illustrative purposes, image sensor 200 features three-phase VCCDs 205, although the same strapping pattern may be applied to CCDs with a different number of phases per pixel. The external V1, V2, and V3 biases (which control the movement of photocharge through the three “phases,” or stages of current flow, of the VCCDs 205) are supplied to the pixel array on bus lines 210, 215, 220, respectively, which are typically formed of a metal such as aluminum or copper. The V1, V2, and V3 biases are electrically connected to phase strapping lines 225, 230, 235 (i.e., strapping lines for the VCCDs 205, where each individual strapping line carries only one phase bias) via contacts 240. While contacts 240 are illustrated as unitary contacts, they may also be formed as arrays of smaller discrete contacts.
The phase strapping lines 225, 230, 235 are typically formed of tungsten, TiW, or aluminum, and, in addition to providing low-resistance electrical conduction, are substantially opaque and thus block unwanted light from entering the VCCDs 205 (and may thus also be referred to as “lightshields”). Such light may generate deleterious additional optical signals within the VCCDs 205 (a phenomenon referred to as “smear”). As shown, the phase strapping lines 225, 230, 235 may be grouped in “bias groups,” where multiple lines conducting the same phase signal neighbor each other. FIG. 2 illustrates bias groups of two. One advantage of increasing the number of phase strapping lines within a bias group is the reduction of the probability that a physical short-circuit within a particular phase strapping line (e.g., due to a processing defect or stray particle) results in an electrical short-circuit in the image sensor itself.
As shown, the phase strapping lines 225, 230, 235 are connected to the V1, V2, and V3 gates 245, 250, 255 (which are typically formed of polysilicon) with contacts 260. Some conventional sensors do not utilize phase strapping lines 225, 230, 235, and instead electrically contact the polysilicon gates 245, 250, 255 at their terminal ends at the left and right side of the pixel array. However, the resistance of the polysilicon gates 245, 250, 255 is typically one to two orders of magnitude greater than the resistance of the phase strapping lines 225, 230, 235, and this vastly increased resistance significantly reduces the frame rate (i.e., the rate at which images can be captured and read out of the device).
The design illustrated in FIG. 2 is often sufficient for small image sensors, in which control signals must propagate only short distances, because the relatively high resistivity of polysilicon gates and control lines has only a minor impact on frame rate. However, as image-sensor size increases, the increasing resistance of the phase strapping lines 225, 230, 235 impacts the characteristic response time, slows device operation, and reduces frame rate. Thus, there is a need for techniques for enabling further decreases in internal resistance in CCD image sensors, particular as sensor sizes continue to increase.